Conventional linear shrinkage of semiconductor devices approaches to lithography and physical limitations. One way to overcome the issues caused by the conventional linear shrinkage is to stack the semiconductor devices three-dimensionally, for example, via chip-to-chip or chip-to-wafer stacking technologies. Another stacking technology applicable, for example, for integrated circuits with memory cells, is a 3D device stacking technology which includes the formation of at least a second single-crystalline semiconductor layer above electronic or micromechanical devices that are formed over and/or in a first single-crystalline semiconductor layer or semiconductor base.
For these and other reasons, there is a need for the present invention.